1. Field
This invention pertains to the field of memory systems, and more particularly, to a memory system and a method of reading and writing data to a memory device that includes mode selection between a dual data strobe mode and a single data strobe mode with data inversion.
2. Description
Generally, it is a goal to improve the data transfer speed of a memory system. To this end, various techniques are employed to improve the high frequency characteristics (speed) of a memory device. In general, there are two types of memory devices: a single DQS (data strobe) mode memory device, and a dual, or differential, DQS (data strobe) mode memory device. In the case of the differential DQS mode memory device, the differential data strobe signals make it possible to improve the high frequency characteristics of the memory device by improving the noise margin. Meanwhile, for the single DQS mode memory device, a data inversion scheme is employed to reduce the simultaneous switching noise in the device and thereby improve the high frequency operating characteristics. Examples of both types of memory devices will now be described in further detail.
FIG. 1 is a block diagram of a conventional memory system 1 with a single DQS memory device 100 and a memory controller 200.
The memory system 1 operates with a data inversion scheme, as follows. During a data write operation, the signals DM<0:3> perform a data masking operation, WDQS<0:3> operate as data strobe signals, and DIM is a data inversion flag in indicating whether or not the data (all four data bytes) should be inverted. During a data read operation, the signals RDQS<0:3> operate as data strobe signals, and DM<0:3> serve as data inversion flags.
FIG. 2 shows an exemplary ball (or pin) configuration of a conventional single DQS mode memory device 1 with the data inversion scheme. As can be seen from FIG. 2, a total of eight separate pins are required for the RDQS<0:3> and WDQS<0:3> data strobe signals.
FIG. 3 shows a data processing block diagram of a conventional single DQS mode memory device 100. The memory device 100 includes data processing circuit 110 for byte0, data processing circuit 120 for byte1, data processing circuit 130 for byte2, data processing circuit 140 for byte3, and memory cell array 150. In the memory device 100, each single bit of the RDQS<0:3> data strobe signals at pins 111, 121, 131 and 141, and the WDQS<0:3> data strobe signals at pins 112, 122, 132 and 142, is dedicated to one data processing unit 110, 120, 130 or 140 for processing one eight-bit byte of data for the memory cell array 150. During a data write operation, DM<0:3> at pins 114, 124, 134, and 144, masks write data for the four data processing circuits 110, 120, 130 and 140. Meanwhile, during a data read operation, each single bit of the DM<0:3> signals is dedicated as a read data inversion flag for one of the data processing unit 110, 120, 130 or 140. On the other hand, during a data read operation, DIM at pin 160 is used as a write data inversion flag for all four data bytes. Four bytes of data comprising DQ<0:31> are input/output at the input/output pins 113, 123, 133 and 143.
FIG. 4 shows a block diagram of the byte0 data processing circuit 110 of the single DQS mode memory device 100. The data processing circuits 120, 130, and 140 in FIG. 3 are configured similarly to data processing circuit 110. The data processing circuit 110 comprises a number of components, including data strobe signal generator 113, data control circuit 114, and data inversion block 115. Data strobe signal generator 113 generates the read data strobe signal RDQS0. Data control circuit 114 controls data input/output during both data read and data write operations. DM0 performs two functions: it masks write data for byte0 during a data write operation, and it serves to output the read data inversion flag R_FLAG0 during a data read operation. Meanwhile, DIM provides the write data inversion flag W_FLAG0 during a data write operation. Data inversion block 115 performs a data inversion process during data read and data write operations according to the logical values of flags R_FLAG0 and W_FLAG, respectively.
FIG. 5 shows a conventional data inversion block 115. The data inversion block 115 includes the data toggle detection circuit 115-1 and the data inversion circuit 115-2. The data toggle detection circuit 115-1 detects whether the read data from the memory cell array 150 are inverted or not, and then outputs the read data inversion flag R_FLAG0 having the corresponding logic state. Data inversion circuit 115-2 inverts the data being written to, or read from, the memory cell array 150 according to the logical value of the W_FLAG in a data write mode, or the R_FLAG0 in a data read mode.
The data inversion block 115 reduces the simultaneous switching noise in the input/output buffers of the memory device 100 and thereby improves the high frequency characteristics of the device.
FIG. 6 shows a conventional data toggle detection circuit 115-1. The data toggle detection circuit 115-1 compares input data DATA_INT<0:7> with a reference terminal having a reference current capability of 3.5 units. If, for example, DATA_INT<0:7> is 11111110, then the node N1 will be pulled down to a logical low state (0), and the output signal R_FLAG0 will be in a logical high state (1). Meanwhile, if DATA_INT<0:7> is 11100000, then the node N1 will be pulled up to a logical high state (1), and the output signal R_FLAG0 will be in a logical high state (0). Accordingly, if the number of bits of DATA_INT<0:7> which are logically high are greater than 4, then R_FLAG0 will be logically high, while if the number of bits of DATA_INT<0:7> which are logically high are less than 4, then R_FLAG0 will be logically low.
FIG. 7 shows a conventional data inversion circuit 115-2. The data inversion circuit 115-2 includes data inverters 116-1, 116-2, 116-3, 116-4, 116-5, 116-6, 116-7, and 116-8. The data inverters 116-2, 116-3, 116-4, 116-5, 116-6, 116-7, and 116-8 in FIG. 7 are configured similarly to data inverter 116-1. During a data read operation, the READ signal closes the switches S5 and S7, while the R_FLAG0 signal closes one of the switches S1 and S2 depending upon whether the corresponding data bit is to be inverted or not. Similarly, during a data write operation, the WRITE signal closes the switches S6 and S8, while the W_FLAG signal closes one of the switches S3 and S4 depending upon whether the corresponding data bit is to be inverted or not.
FIG. 8 shows a timing diagram of a single DQS mode memory device with a data inversion scheme. In particular, the timing diagram of FIG. 8 shows a single DQS mode memory device with so-called “Burst-4” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from FIG. 8, read data (Q0, Q1, Q2, and Q3) are output from the memory device in sync with the rising edge of RDSQ0. Meanwhile, write data (D0, D1, D2, and D3) are input to the memory device in sync with the center of the WDQS0 pulses (center strobing). Furthermore, DM0 operates as a read data inversion flag during data read operations, and to mask write data during data write operations. DIM operates as a write data inversion flag during data write operations.
Accordingly, operation of a conventional memory system 1 with a single DQS memory device 100 operating with data inversion and a memory controller 200 has now been explained in relevant part with respect to FIGS. 1-8.
As mentioned above, there is also another type of memory system employing a dual, or differential, DQS mode memory device.
FIG. 9 shows a block diagram of a conventional memory system 2 with a differential DQS mode memory device 300 and a memory controller 400.
The differential DQS<0:3> and /DQS<0:3> signals operate as data strobes during both data read and data write operations. During a data write operation, the signals DM<0:3> perform a data masking operation. Because the differential DQS mode memory device 300 does not employ data inversion, there is no need for the DIM pin in the differential DQS mode memory device 300.
FIG. 10 shows an exemplary ball (or pin) configuration of a conventional differential DQS mode memory device 400. As can be seen from FIG. 9, a total of eight separate pins are required for the DQS<0:3> and /DQS<0:3> data strobe signals.
FIG. 11 shows a data processing block diagram of a conventional differential DQS mode memory device 300. The differential DQS mode memory device 300 includes data processing circuit 310 for byte0, data processing circuit 320 for byte1, data processing circuit 330 for byte2, data processing circuit 340 for byte3, and memory cell array 350. In the memory device 300, each single bit of the IDQS<0:3> data strobe signals at pins 311, 321, 331 and 341, and the DQS<0:3> data strobe signals at pins 312, 322, 332 and 342, is dedicated to one data processing unit 310, 320, 330 or 340 for processing one eight-bit byte of data for the memory cell array 350. During a data write operation, DM<0:3> at pins 314, 324, 334, and 344 masks write data for the four data processing circuits 310, 320, 330 and 340. Four bytes of data comprising DQ<0:31> are input/output at the input/outputs 313, 323, 333 and 343.
FIG. 12 shows a block diagram of a conventional byte0 data processing circuit 310. of the single DQS mode memory device 300. The data processing circuits 320, 330, and 340 in FIG. 11 are configured similarly to data processing circuit 310. The data processing circuit 310 comprises a number of components, including data strobe signal control circuit 313 and data control circuit 314. Data strobe signal generator 313 generates the data strobe signals DQS0 and /DQS0 during data read operations, and receives the data strobe signals DQS0 and /DQS0 during data write operations. Data control circuit 314 controls data input/output during both data read and data write operations. DM0 masks write data during a data write operation.
FIG. 13 shows a timing diagram of a differential DQS mode memory device without a data inversion circuit. In particular, the timing diagram of FIG. 13 shows a differential DQS mode memory device with so-called “Burst-4” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from FIG. 13, read data (Q0, Q1, Q2, and Q3) are output from the memory device in sync with the rising edge of RDSQ0. Meanwhile, write data (D0, D1, D2, and D3) are input to the memory device in sync with the center of the WDQS0 pulses (center strobing). Furthermore, DM0 is provided to mask write data during data write operations.
FIGS. 39-41 are provided to help explain how the dual (differential) DQS mode memory device and the single DQS mode memory device with a data inversion scheme can have improved high frequency characteristics (speed) compared to a single DQS mode memory device without data inversion. FIG. 39 shows a timing diagram of a read operation of a single DQS mode memory device, FIG. 40 shows a timing diagram of a read operation of a dual (differential) DQS mode memory device, and FIG. 41 shows a timing diagram of a read operation of a single DQS mode memory device with a data inversion scheme. In FIGS. 39-41, “MD” means “memory device,” and “MC” means “memory controller.” In each case, the memory controller receives data (DQ's) accompanied with a data strobe signal (DQS). The windows tS1 and tH1 are timing margins for the data DQ's and the data strobe signal DQS.
FIGS. 39-41 illustrate how a dual (differential) DQS mode memory device improves the high frequency characteristics by decreasing the invalid regions of the DQS signal. Meanwhile, the single DQS mode memory device improves the high frequency characteristics by decreasing the invalid regions of the DQ's.
As can be seen above, the configuration and operation of a memory system with the single DQS memory device employing the data inversion scheme are significantly different from the configuration and operation of a memory system with the differential DQS memory device. Depending upon the memory system, the proper memory device must be employed. That is, a single DQS memory system designed to employ data inversion will not properly operate with a differential DQS memory device without a data inversion circuit. Similarly, a differential DQS memory system without data inversion will not properly operate with a single DQS memory device with a data inversion circuit.
Accordingly, it would be advantageous to provide a method and memory system that can operate in both a single DQS mode with data inversion, and in a dual, or differential, DQS mode. It would also be advantageous to provide a memory device capable of operating with both a single DQS memory system designed to employ data inversion, and with a differential DQS memory system without data inversion. Other and further objects will appear hereinafter.
The present invention is directed toward a method and memory system that can operate in both a single DQS mode with data inversion, and in a dual DQS mode.
In one aspect of the invention, a memory system comprises: a memory device having a memory cell array adapted to store data and a data inversion circuit adapted to selectively invert the data when it is written into and read from the memory cell array; a controller connected to the memory device and adapted to write the data into the memory device and to read the data out of the memory device in response to data strobe signals; and data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode. In the first data strobe mode, the data strobe signals comprise a write data strobe signal for writing data into the memory device and a read data strobe signal for reading data from the memory device. In the second data strobe mode the data strobe signals comprise a pair of differential data strobe signals for writing data into and reading data from the memory device.
In another aspect of the invention, a memory device comprises: a memory cell array adapted to store data; a data input/output (I/O) bus through which the data is written into and read from the memory device; a data inversion circuit adapted to selectively invert the data when it is written into and read from the memory cell array; and data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode, a second data strobe mode, and a third data strobe mode. In the first data strobe mode, the data strobe signals comprise a write data strobe signal for writing data into the memory device and a read data strobe signal for reading data from the memory device and the data inversion circuit is controlled to selectively invert the data. In the second data strobe mode, the data strobe signals comprise a pair of differential data strobe signals for writing data into and reading data from the memory device without any data inversion. In the third data strobe mode, the data strobe signals comprise a pair of differential data strobe signals for writing data into and reading data from the memory device, and the data inversion circuit is controlled to selectively invert the data.
In yet another aspect of the invention, a memory system comprises: a memory device having a memory cell array adapted to store data in a plurality of data words, wherein each data word comprises a plurality of data bytes; and a controller connected to the memory device and adapted to write the data into the memory device and to read the data out of the memory device, wherein the memory device further comprises means for selectively inverting individual bytes of the data when the data is written into and read from the memory cell array.
In still another aspect of the invention, a memory device comprises a memory cell array adapted to store data in a plurality of data words, wherein each data word comprises a plurality of data bytes, and means for selectively inverting individual bytes of the data when the data is written into the memory cell array.
In a further aspect of the invention, a method of writing data to a memory cell in a memory device, wherein the data comprises a plurality of data words and each data word comprises a plurality of data bytes, comprises receiving a data word at a data input of the memory device; receiving a plurality of write data inversion flags at the memory device, each write data inversion flag indicating whether a corresponding byte of the received data word should be inverted; selectively inverting individual bytes of the received data word according to the write data inversion flags; and writing the selectively inverted data word into the memory cell.
In yet a further aspect of the invention, a method of outputting data to be written to a memory cell comprises: selectively inverting individual bytes of a data word; setting a plurality of write data inversion flags, each write data inversion flag indicating whether a corresponding byte of the data word is inverted; outputting the selectively inverted data word; and outputting the plurality of write data inversion flags.
In a still further aspect of the invention, a method of communicating data between a controller and a memory device, wherein the data comprises a plurality of data words and each data word comprises a plurality of data bytes, comprises: selectively inverting individual bytes of a data word; setting a plurality of write data inversion flags, each write data inversion flag indicating whether a corresponding byte of the data word is inverted; outputting the selectively inverted data word; outputting the plurality of write data inversion flags; receiving the selectively inverted data word at a data input of the memory device; receiving the plurality of write data inversion flags at the memory device; selectively inverting individual bytes of the received data word according to the write data inversion flags; and writing the selectively inverted received data word into a memory cell array of the memory device.
Further aspects will become evident in the detailed description to follow.